Cadence Allegro and OrCAD 17.20.000-2016 HF053(54)
Cadence Allegro and OrCAD 17.20.000-2016 HF053(54) | 7.7 Gb
Cadence Design Systems, Inc. has released an update (HF053 & HF054) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.000-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
CCRID Product ProductLevel2 Title
2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools->Reports when there is a space present in the textpath variable
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6
2050674 APD PARTITION Cannot remove C-Point from a partitioned design
2068814 APD WIREBOND Bond wires cross on auto-separate
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
2038021 PSPICE FRONTENDPLUGI Bias display is not updated
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project
About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors' productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
-
Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.
Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF053(054)
Supported Architectures: x64
Website Home Page :
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 7.7 Gb
Download link:
Код:
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