Cadence Allegro and OrCAD 17.20.000-2016 HF052 | 3.7 GbCadence Design Systems, Inc. has released an update (HF052) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.000-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
CCRID Product Product Level 2 Title
2020429 ADW ADWSERVER Incorrect adwservice status on Linux
2034815 ADW LIBDISTRIBUTI Cannot mark classification obsolete because it is associated to objects in the database
2015461 ADW PART_BROWSER New Component Browser should read the mapping of symbol and associated package as it results in error PKG-1005
2049380 ADW PART_BROWSER System Capture Import HDL not importing complete PTF File data
1948608 ADW TDA CUSTOMVAR directive value in project CPM was not updated by TDA UPDATE command.
1992662 ADW TDA Custom directive added to the cpm file not updated after check-in
1733129 ALLEGRO_EDITOR COLOR 'Display - Highlight', double-click permanently highlights symbol
1861938 ALLEGRO_EDITOR COLOR Changing layer color changes layer visibility
2034753 ALLEGRO_EDITOR CROSS_SECTION Allegro PCB Editor crashes when a cross-section technology file is imported in Overwrite mode
2036895 ALLEGRO_EDITOR CROSS_SECTION Replay script error during import of tcfx Xsection file
1929360 ALLEGRO_EDITOR DATABASE Via color is inconsistent on Vias with color assigned
1984203 ALLEGRO_EDITOR DATABASE Drill holes not displayed correctly in the Zone area
2013596 ALLEGRO_EDITOR DATABASE Assigning net name on Vias does not change the Via Color to that on Net Color automatically
2025798 ALLEGRO_EDITOR DATABASE Assign net to via changes color of the via to the default color
2032678 ALLEGRO_EDITOR DATABASE Unable to delete layer on design
2032725 ALLEGRO_EDITOR DATABASE Dehighlight removes color assignment from color dialog
2029542 ALLEGRO_EDITOR DFA Interactive Placement with Manufacturing Package to Package spacing
2020548 ALLEGRO_EDITOR DFM Cadence DFM Customer site cannot Submit Request
2020566 ALLEGRO_EDITOR DFM Error when sending Design True DFM Rules Request
2030179 ALLEGRO_EDITOR DFM Allegro PCB Editor .brd file will not save after routing using Automatic Router
2052907 ALLEGRO_EDITOR DFM The Submit Request button for DesignTrue DFM Rules Request does not work
1928915 ALLEGRO_EDITOR EDIT_ETCH PCB Editor constraint status bar does not match Constraint Manager data when z-axis delay is turned on.
1932165 ALLEGRO_EDITOR EDIT_ETCH Arc slide behavior with clines at odd angles: notches on slides
1943901 ALLEGRO_EDITOR EDIT_ETCH arc segment incorrect on slide.
2031055 ALLEGRO_EDITOR EDIT_ETCH On drawing cline the width on a Layer is larger than defined constraint
1877891 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor crashes when started from EDM for projects without a board file or empty master.tag file
2040689 ALLEGRO_EDITOR NC The decimal digits of a rotated oval padstack do not match the Drill Chart.
2028105 ALLEGRO_EDITOR PLACEMENT Delay in moving a large count pin symbol
2019027 ALLEGRO_EDITOR REPORTS Information shown in the Report Viewer is not correct.
2022461 ALLEGRO_EDITOR SHAPE Abnormal termination of thieving function in Allegro PCB Editor
2032048 ALLEGRO_EDITOR SHAPE shape void difference from hotfix 026 to 048: need square corners for full round
2040138 ALLEGRO_EDITOR SHAPE shape_rki_autoclip affects the overlapping shape boundary
2040259 ALLEGRO_EDITOR SHAPE Same net shape and cline adds shape void around cline
2031468 ALLEGRO_EDITOR TECHFILE Cross section import (.tcfx) not working correctly.
2006425 ALLEGRO_EDITOR UI_FORMS Option to disable 'Create a New Design' window in OrCAD PCB Designer
2007451 ALLEGRO_EDITOR UI_FORMS Option to suppress 'Create a New Design" window for File > Open in OrCAD PCB Editor from hotfix 048
2009314 ALLEGRO_EDITOR UI_FORMS Existing scripts that open OrCAD PCB Editor not working in hotfix 048
2021476 ALLEGRO_EDITOR UI_FORMS PCB Editor is slow when using the command 'add connect'
2039462 ALLEGRO_EDITOR UI_FORMS Hovering over Default symbol height in Design Parameter Editor does not display a description
1808054 ALLEGRO_EDITOR UI_GENERAL Illegal value in axlFormSetField crashes PCB Editor
1822679 ALLEGRO_EDITOR UI_GENERAL 'Symbol pin #' field is truncated on rotating components in the Placement Edit mode
1856438 ALLEGRO_EDITOR UI_GENERAL Script recording messages not displayed in the PCB Editor task bar when using the script window.
1879078 ALLEGRO_EDITOR UI_GENERAL Running PCB Editor from command prompt with '-product help' should list all products and options
1944225 ALLEGRO_EDITOR UI_GENERAL Cannot close log file window till we close report dialog box
1967708 ALLEGRO_EDITOR UI_GENERAL New Command Window Shows Last Command in UI
1968380 ALLEGRO_EDITOR UI_GENERAL Write all open editing sessions in MRU
1982138 ALLEGRO_EDITOR UI_GENERAL axlFormListDeleteItem(fw field -1) not deleting last item of a list
2003054 ALLEGRO_EDITOR UI_GENERAL Grids not shown when 'nolast_file' is set
2010760 ALLEGRO_EDITOR UI_GENERAL Pressing tabs is selecting only vias and not selecting clines in PCB Editor in hotfix 048
2019120 ALLEGRO_EDITOR UI_GENERAL Tab key is not working when there are two objects on top of each other
2029248 ALLEGRO_EDITOR UI_GENERAL Colorview load is not working when using absolute path
2030985 ALLEGRO_EDITOR UI_GENERAL The view of the PCB is offset after closing and opening the board.
2037968 ALLEGRO_EDITOR UI_GENERAL Tab key will not cycle between cline elements.
2015766 ALLEGRO_PROD_TOOLB CORE Advanced Testpoint Check does not work
2023356 ALLEGRO_PROD_TOOLB CORE Edit new session does not work in quick symbol editor tool box
2017162 CAPTURE CONSTRAINT_MG Cannot apply ECSets in Constraint Manager-enabled Capture
2026777 CAPTURE CONSTRAINT_MG Cannot apply electrical CSet (ECSet) in Constraint Manager-enabled Design Entry CIS
2027545 CAPTURE CONSTRAINT_MG Getting error (ORCAP-40320) while creating ECSet
2012967 CAPTURE OTHER Capture license is loaded slowly in hotfix 048
2010093 CONCEPT_HDL ARCHIVER Archive .zip file keeps the whole folder hierarchy and not only the project hierarchy
2040431 CONCEPT_HDL EDIF300 EDIF300, Schematic Writer, crashes in release 17.2-2016
2034077 SIP_LAYOUT DFA DRC is not catching all Shape minimum width violations
2034094 SIP_LAYOUT DIE_ABSTRACT_ [VSDP-RDL Exchange] some traces are lost in SiP Layout
2037462 SIP_LAYOUT DIE_ABSTRACT_ Cline Segments are lost on saving and re-opening the design in next session
2025321 SIP_LAYOUT IMPORT_DATA compose symbol from geometry defaults need to change due to performance
2017759 SIP_LAYOUT PLACEMENT Placing a die creates extra place bound and puts pin numbers in the wrong place, causing future netlist import failure
2021057 SIP_LAYOUT SHAPE Polybool assert error when adding dynamic shape prevents shape voiding.
2012381 SIP_LAYOUT SKILL Ability to check if the Dynamic Unused Pads Suppression box is selected using SKILL
1990299 SIP_LAYOUT UI_GENERAL Pressing 'Esc' cancels DRC checking when there is no focus on the Allegro PCB Editor canvas
1997317 SIP_LAYOUT WLP Advanced WLP, Metal Density Scan does not correctly calculate scan region count in Y direction
2029524 SPECCTRA ROUTE SPECCTRA stops responding when executing the quit command
1670888 SYSTEM_CAPTURE CANVAS_EDIT Rotation error when connected to a power symbol
1880809 SYSTEM_CAPTURE CANVAS_EDIT Can modify only one RefDes from canvas for duplicate RefDes; can modify both from the Properties window
1979063 SYSTEM_CAPTURE CANVAS_EDIT System Capture : File > Close is grayed out
2034498 SYSTEM_CAPTURE CAPTURE_IMPOR Cannot find parts via Find & Replace after importing Capture design
1984561 SYSTEM_CAPTURE CROSSPROBE System Capture: Cross-probing from layout does not work when zoomed into a specific area on canvas
1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
2025876 SYSTEM_CAPTURE EDIT_OPERATIO Route failures when dragging a circuit
2005904 SYSTEM_CAPTURE FORMAT_OBJECT Pin name text is smaller in System Capture than in DE-HDL by about 25%
2036782 SYSTEM_CAPTURE IMPORT_BLOCK Unable to import the block from project.
2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture
2025950 SYSTEM_CAPTURE IMPORT_DEHDL_ Broken connectivity on imported ground symbols
2040923 SYSTEM_CAPTURE MISCELLANEOUS System Capture - Multiple Symbol Replace, disconnects and changes orientation
2017526 SYSTEM_CAPTURE NAVLINKS Page information missing in NAVLINKS
2015346 SYSTEM_CAPTURE PAGE_MANAGEME Rename page fails in some cases
2038811 SYSTEM_CAPTURE PRINT Black & White PDF showing colors
2048493 SYSTEM_CAPTURE SYMBOL_GEN Symbol Editor, Modify outline adds an 'X' in symbol incorrectly
2031995 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor does not load the design and restarts the machine after sometime.
2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
1968431 SYSTEM_CAPTURE WORKSPACE Unable to reorder the pages (tabs) when opened in the workspace
2040995 XTRACTIM GUI Running XIM from APD enables "skip DC R simulation" by mistake
About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors' productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
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Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.
Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF052
Supported Architectures: x64
Website Home Page :
Код:
http://www.cadence.com
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 3.7 Gb
Download link:
Код:
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