Cadence SPB OrCAD 16.60.042 Hotfix (February 22, 2015)

Cadence SPB OrCAD 16.60.042 Hotfix (February 22, 2015)

Cadence SPB OrCAD 16.60.042 Hotfix | 1.1 Gb

Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released an hotfix 42 for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.


Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.

This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry's first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.

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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
1349849 CIS OTHER Capture crashes on generating variant reports
1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
1350477 PSPICE SIMULATOR RPC server is unavailable
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.

About Cadence Design Systems, Inc.

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

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